============================================================== Guild: wafer.space Community Channel: ℹ️ - Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 2025-08-31 11:59 p.m. Before: 2025-10-01 12:00 a.m. ============================================================== [2025-09-04 9:24 p.m.] mithro_ @Tholin / @Tim Edwards - I'm hoping to work with @Leo Moser (mole99) to put together something using previous MPW designs to send to GF for testing very soon. [2025-09-04 9:26 p.m.] tholin Like, this month? [2025-09-04 9:55 p.m.] mithro_ Yes [2025-09-04 9:55 p.m.] mithro_ Hopefully that isn't a surpise to @Leo Moser (mole99) 🙂 [2025-09-04 10:08 p.m.] tholin Its was a surprise to me, heh [2025-09-04 10:09 p.m.] tholin Would you also be interested in sending one of the WiP custom padframes to GF for testing? [2025-09-04 10:52 p.m.] mithro_ Sure! I believe @Leo Moser (mole99) is busy this week with finishing iHP related stuff? [2025-09-04 11:03 p.m.] tholin I have a padframe that should be working. [2025-09-04 11:05 p.m.] tholin I can take that, populate the project area with a copy of one of my GFMPW designs and we'll see if everything still works as before. [2025-09-04 11:05 p.m.] tholin Would allow me to do some fixes as well. The RISC-V core on my multi-project die is just a few adjustments/bugfixes away from being able to boot Linux. [2025-09-05 12:03 a.m.] tholin @Tim 'mithro' Ansell Would this be of interest to you in general? Linux-capable CPU core on gf180? [2025-09-05 12:04 a.m.] mithro_ A bit weird but I definitely wouldn't say no. [2025-09-05 12:08 a.m.] mithro_ The uclinux on Tiny Tapeout is a pretty good demo to show people. [2025-09-05 3:54 p.m.] mole99 The idea is to get early feedback from GF, especially regarding the sealring, as the corner of the sealring is simply "best-effort" since we don't have any rules for it in the PDK. Another issue is fill generation, for which we currently only have a partial implementation in magic. I'm just finishing up my IHP tapeout and will be at ORConf right after that. After ORConf, I will have one full week to create a test reticle and work on fill. I will also upload the template repository for wafer.space designs. I would appreciate if you could use the template to build your chip @Tholin. It automatically adds the sealring after GDS streamout. [2025-09-05 4:01 p.m.] tholin Alright, will do [2025-09-05 4:02 p.m.] tholin I'm rushing some bugfixes to my multi-project die right now, and then I will tape that out a second time. [2025-09-05 4:03 p.m.] tholin Not gonna do anything new. The multi-project die is a whole heap of designs that I already know the characteristics of, which is good. [2025-09-05 4:11 p.m.] mole99 Thanks! I'll let you know after ORConf once it's pushed. Being able to make comparisons between previous shuttles is definitely good. [2025-09-05 6:21 p.m.] rtimothyedwards_19428 @Tholin : I'm glad you're working on a 3.3V standard cell library for GF180MCU. I have come to the conclusion that the OSU standard cells are invalid and probably will never be synthesizable. I think it is the same old story with academic development---At one time in the past, they had expertise in standard cell design, but that expertise has been lost, and now all they do is academic excercises like CharLib where they are concerned about simulation efficiency and accuracy, and nobody has noticed that the layouts they're passing to the tool are unworkable for a variety of reasons (such as, for example, having a cell height that is not divisible by any track height). [2025-09-05 6:27 p.m.] tholin Yeah! I do need to keep working on it sometime. Its on hold for now until after the first wafer.space shuttle. [2025-09-06 8:15 a.m.] mole99 @Tholin Just so you know, final submission will be in early December, so there may still be time to work on it :) [2025-09-06 3:13 p.m.] tholin True, but my SCL is 3.3V and I do wish to tape out one more 5V chip on the first wafer.space shuttle. [2025-09-06 3:14 p.m.] tholin Second and onwards I will be playing with 3.3V. Lets uhhh...make sure that the 5V stuff we have already works first. [2025-09-06 3:14 p.m.] tholin Oh, that *just* reminds me that I should absolutely create a test layout for the extra 5V cells I’m making. [2025-09-08 11:45 p.m.] mithro_ @everyone - The CrowdSupply page which will allows you to purchase wafer.space slots will be live in the next day or two. I am looking for people who want to purchase a slot to be beta testers. {Reactions} ‼️ (4) 🚀 (4) [2025-09-09 1:43 a.m.] ombudsman Hey @Tim 'mithro' Ansell which pdk will we be using? [2025-09-09 1:45 a.m.] mithro_ The gf180mcu PDK (https://gf180mcu-pdk.readthedocs.io/) - I believe at least @Leo Moser (mole99) & @Tholin, @tnt have already been working with it. {Reactions} 👍 (2) [2025-09-09 1:50 a.m.] mithro_ I believe `ciel` is the best way to get the PDK? [2025-09-09 1:51 a.m.] algofoogle Exciting times, Tim 🙂 {Reactions} blobsignyes [2025-09-09 3:04 a.m.] always_ff_rohan yeah, with sky130 I use this - ``` #Enable PDK with this commit ciel enable --pdk-family sky130A 12df12e2e74145e31c5a13de02f9a1e176b56e67 # Initiate the flow from design directory librelane --ciel-pdk -p sky130A -s sky130_fd_sc_hd --flow Classic config.json ``` [2025-09-09 3:05 a.m.] always_ff_rohan GF180 is also same I think [2025-09-09 3:14 a.m.] essen__ Hi guys, I was told this was the place to be and you where looking for beta testers. Still need to give it some more though as to if I wish to commit 6k to my broken a0 👋 [2025-09-09 11:54 a.m.] polyfractal heyo, connected with Tim at OpenSauce and might have roped me into participating as well 🙂 In the middle of a big cross-country move right now (and have no layout experience past my own little DIY projects) so not sure if I'll make this first shuttle. Was thinking about doing some test structures / circuits for an analog'y neuromorphic chip (spiking neural net stuff) [2025-09-10 9:23 a.m.] algofoogle I wish I had the personal budget for a whole die, but in the meantime if anyone is thinking of sharing the cost for a multi-project die, I would at least like to know 🙂 [2025-09-10 2:10 p.m.] essen__ Hi @algofoogle (Anton Maurovic) How much area would you be looking for, and do you have any specific requirements ? [2025-09-10 3:42 p.m.] mithro_ If anyone is ready to order, please contact me with an email address and I'll add you to the access list. [2025-09-10 5:06 p.m.] mithro_ Can people test if https://buy.wafer.space sends them to https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/ correctly? {Embed} https://buy.wafer.space/ wafer.space GF180MCU Run 1 Fabricate 1,000 chips of your own design 2025-09_media/gf180mcu-gelpack-dice_jpg_project-main-8DB90.jpg {Embed} https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/ wafer.space GF180MCU Run 1 Fabricate 1,000 chips of your own design 2025-09_media/gf180mcu-gelpack-dice_jpg_open-graph-DE679.jpg {Reactions} 👍 (3) 💜 [2025-09-10 5:07 p.m.] tholin Tested on Firefox and Edge. Re-direct works. {Reactions} 👆 [2025-09-10 5:09 p.m.] urish Works for me (Chrome) [2025-09-10 5:10 p.m.] urish Nice campaign page! [2025-09-10 5:38 p.m.] mithro_ As I mentioned, anyone ready to commit to a slot, please message me and I'll get you added to the ability to purchase right away. [2025-09-11 4:48 a.m.] algofoogle Started a thread. [2025-09-11 6:24 a.m.] 246tnt @Tim 'mithro' Ansell In the campaign page, maybe specify it's the `gf180mcuD` variant in the PDK, that should allow people to lookup anything they need about the exact spec ( like top metal thickness for instance ). {Reactions} ➕ [2025-09-11 7:15 a.m.] mole99 Also "GlobalFoundries GF180MCU open‑source PDK" should be "GlobalFoundries gf180mcu open‑source PDK" or "GlobalFoundries open‑source PDK for GF180MCU". [2025-09-15 9:24 p.m.] rtimothyedwards_19428 @Tholin : Would it be okay with you if I incorporated your `gf180mcu_as_sc_mcu7t3v3` standard cells into the open_pdks build of GF180MCU as an option? I would like to put something on the 1st wafer.space shuttle run using this library. [2025-09-15 9:27 p.m.] tholin Okay, full disclaimer first: I never ran the full prechecks on a layout produced with the SCL. I don't know if it produces DRC correct GDSII outputs in the eyes of klayout (which was a massive pain point with my other SCL). [2025-09-15 9:28 p.m.] rtimothyedwards_19428 I understand the risks, and I'm willing to run the whole library through a large project synthesis and debug anything that looks wrong. Maybe extend the library, as well. [2025-09-15 9:28 p.m.] rtimothyedwards_19428 I want a 3.3V standard cell library for gf180mcu, and OSU is not going to be it. [2025-09-15 9:29 p.m.] tholin Yeah, I'm not surprised {Reactions} 😆 [2025-09-15 9:29 p.m.] mithro_ Hi everyone, I'm in the US/Chicago time zone until the 5th October [2025-09-15 9:30 p.m.] mithro_ @Tim Edwards - @Leo Moser (mole99) talked with Staf from chips4makers at OrConf and apparently his cells should work on GF180MCU [2025-09-15 9:32 p.m.] tholin I know Tim Ansell wants to do a test tapeout with GF later this month and for his consideration I'm gonna offer a GDSII of my multi-project die, but with some minor bugs fixed and using the template that mole99 is cooking up. After this, I'll be mostly free to keep developing my 3.3V SCL. [2025-09-15 9:38 p.m.] rtimothyedwards_19428 @Tim 'mithro' Ansell : If you want people to have access to Staf's cells (SRAM, or does he have more?), then I just need a pointer to a repository and I can incorporate them into open_pdks for GF180MCU. [2025-09-15 9:39 p.m.] mithro_ @Tim Edwards - I'm guessing @Leo Moser (mole99) is probably still travelling back from OrConf at the moment. [2025-09-15 9:42 p.m.] mithro_ This is what @Leo Moser (mole99) sent me; > I'm now back from ORConf, which was great! I had some interesting discussions with a lot of people. > > One of the most interesting projects for us is Staf Verhaegen's SRAM compiler: https://www.youtube.com/watch?v=G9uyKw3XoiM > It would not only allow us to generate SRAM macros in different configurations, but also for 3.3V transistors on gf180mcu. > > I asked him if he would be interested to put different SRAM configurations on a shuttle slot. He is interested, although there are some changes needed to make it work on gf180mcu. > I told him I'll get back to him after asking you whether there's still a slot available. > > Moreover, we could also use Staf's FlexCell stdcell generator to generate 3.3V cells. https://gitlab.com/Chips4Makers/c4m-flexcell > > Tholins cells are great, but this would give us a larger set of stdcells that we could even take to a different process. Tamas did not use them for the TT test shuttle only because he couldn't get them working with LibreLane in time for the tapeout. But it's just a matter of figuring out how to configure LibreLane with these stdcells. > > The only missing part then is the separation of the 5V and 3.3V voltage domains in the padring. There's a clever workaround using breaker cells that Tamas has already used. The proper way would be to create new power/ground pad cells based on the existing ones. {Embed} FOSSi Foundation https://www.youtube.com/watch?v=G9uyKw3XoiM A portable area efficient SRAM compiler: a ... job somebody has to ... For developing a SRAM compiler that is area efficient and performant expertise is needed but above all a lot transpiration and persistence; more so I would say than other circuits. Luckily we (e.g. ChipFlow) is developing one for IHP and their SG13G2 open source process. This work is done in the FlowSpace project funded by the German government.... 2025-09_media/maxresdefault-CA679.jpg {Embed} https://gitlab.com/Chips4Makers/c4m-flexcell Chips4Makers / c4m-flexcell · GitLab A flexible, scalable, open source standard cell library. 2025-09_media/twitter_card-570ddb06edf56a2312253c5872489-60AF3.jpg [2025-09-15 9:43 p.m.] mithro_ His stuff is also listed at https://bit.ly/ws-gf180mcu-stdcells {Embed} https://bit.ly/ws-gf180mcu-stdcells wafer.space - Notes around voltages and options for I/O and standar... Notes around voltages and options for I/O and standard cells bit.ly/ws-gf180mcu-stdcells Voltages and GF180MCU See also https://bit.ly/ws-gf180 The GF180MCU process uses the same stack as the other 180nm process technologies but changes; The default oxide to be the same as the other 180nm proce... 2025-09_media/AHkbwyJe1agTFR-diddXHLe4QsUKu6Ea4uFT63gtAw-A643A [2025-09-15 9:51 p.m.] rtimothyedwards_19428 @Tim 'mithro' Ansell : I have already declared my intent to work on the dual voltage I/O library problem. [2025-09-15 10:13 p.m.] mithro_ @Tim Edwards - Great! Just trying to make sure everyone knows about things. [2025-09-16 7:02 a.m.] mole99 @Tholin Thanks for working on your design so we can include it in the test tapeout. Just to be clear, this is not a real tapeout, but rather a way for us to get feedback from GF about the design of the reticle, the sealring, if the fill matches density also on their side etc. The more real world design we have on there, the better. We should probably call it a virtual tapeout :) [2025-09-16 7:03 a.m.] mole99 @Tim Edwards Great! From what I understand we need two copies of the power and ground cells each, where one is for the core domain and one for the I/O domain. It would be really helpful if you could take a look at this 👏 For now, Tamas used a nice trick to get separate power domains using custom breaker cells, see: https://github.com/TinyTapeout/tinytapeout-gf-0p1/blob/main/docs/padframe.svg However, if we have proper power/ground cells for both domains then we wouldn't have to resort to such tricks. If you have a PR ready just ping me and I can give it a try. We need to make sure that the pin shape for the bondpad comes first in the LEF, so that OpenROAD will promote the correct pin to a BTerm. See this commit: https://github.com/wafer-space/gf180mcu/commit/eb701885d4fc3aff546c974df1b3e7bcce6bd3c7 [2025-09-16 7:09 a.m.] mole99 Yes, we would like to get Staf's FlexCell stdcells into the PDK, as well as his SRAMs. Since both are generated, there's no repository at the moment that hosts the cells afaik. It would probably make sense for wafer.space to host repositories for both, which we keep up to date that you can then incorporate into open_pdks (unless Staf wants to host them himself). [2025-09-16 12:41 p.m.] tholin I made a better DFF to fit into the 7-track 5V SCL. Its slightly wider and has some met2 obstructions, but is significantly faster than the DFFs that ship with the SCL. [2025-09-16 12:41 p.m.] tholin https://cdn.discordapp.com/attachments/1299769089220284467/1417488167581515857/image.png?ex=68caaa3a&is=68c958ba&hm=c03bbb239d8e5bb97ab8df647c00f7970b70be0423f2ef314d7568e0cb7af515& {Embed} https://cdn.discordapp.com/attachments/1299769089220284467/1417488167581515857/image.png?ex=68caaa3a&is=68c958ba&hm=c03bbb239d8e5bb97ab8df647c00f7970b70be0423f2ef314d7568e0cb7af515& 2025-09_media/image-78FE1.png [2025-09-16 12:42 p.m.] tholin Seeing clock period improvements of up to several ns using this. {Reactions} blobclap (2) [2025-09-16 3:05 p.m.] rtimothyedwards_19428 Where can I grab this to incorporate it into the existing standard cells? [2025-09-16 3:07 p.m.] rtimothyedwards_19428 This is a digital standard cell layout made with Tholin's 3.3V standard cells, installed into the PDK with open_pdks and run through librelane. It was almost ludicrously easy. {Attachments} 2025-09_media/ffra-C18BF.png [2025-09-16 3:07 p.m.] tholin Oh good, I expected it to completely break with librelane without major config changes. [2025-09-16 3:09 p.m.] tholin Set `SYNTH_STRATEGY: DELAY 4` if you wanna push it to its limits. [2025-09-16 3:10 p.m.] rtimothyedwards_19428 It was almost perfect out-of-the-box. All I was missing was the "drc_exclude.cells" file, and I had to add a "touch" command to the installer to force it to be created. I'll give "SYNTH_STRATEGY: DELAY 4" a try. This was really just a proof-of-concept test, though. [2025-09-16 3:15 p.m.] rtimothyedwards_19428 "SYNTH_STRATEGY: DELAY 4" apparently worked (?). I'm not sure how to prove that it did. Anyway, at this point it's more productive for me to be pushing my commit to open_pdks. [2025-09-16 3:18 p.m.] tholin That option makes it optimize for pure speed! Should be able to push the clock period real low now. [2025-09-16 3:43 p.m.] tholin I committed a blank drc_exclude.cells file into the SCL’s repo [2025-09-16 3:43 p.m.] tholin So that should be taken care of now [2025-09-16 4:00 p.m.] tholin https://github.com/AvalonSemiconductors/gf180mcu_extra_cells {Embed} https://github.com/AvalonSemiconductors/gf180mcu_extra_cells GitHub - AvalonSemiconductors/gf180mcu_extra_cells: Additional 7-tr... Additional 7-track, 5V standard cells for gf180mcu PDK. - AvalonSemiconductors/gf180mcu_extra_cells 2025-09_media/gf180mcu_extra_cells-C3B07 [2025-09-16 4:00 p.m.] tholin Its in here [2025-09-16 4:01 p.m.] tholin gf180mcu_extra__dfxtp_2 [2025-09-16 5:18 p.m.] rtimothyedwards_19428 Should I merge this directly into the `gf180mcu_fd_sc__` repository, or should I try to incorporate it as an extension (like I did with the "sky130_ef_sc" cells), in which case I would prefer a more targeted library name, like `gf180mcu_as_sc_9t5v0`? [2025-09-16 5:27 p.m.] tholin It should be an extension [2025-09-16 5:27 p.m.] tholin I mean, that's why I called it "extra cells" [2025-09-16 5:28 p.m.] tholin The DFF I made is meant to be a full replacement for the one in the fd_sc_7t5v0, though, and you have the exclude the whole wildcard of `gf180mcu_fd_sc_7t5v0__dff*` from synthesis. [2025-09-16 8:18 p.m.] mithro_ I think a `gf180mcu_as_sc_9t5v0` makes the most sense? [2025-09-16 8:26 p.m.] tholin 7t [2025-09-16 8:26 p.m.] tholin Its still 7-track [2025-09-16 8:26 p.m.] tholin I'm also reserving that name for if/when I make a full 5V custom SCL [2025-09-16 8:27 p.m.] tholin Addons to the existing SCLs should have a separate naming convention. [2025-09-16 8:31 p.m.] mithro_ I would say that everything under `gf180mcu_as_XXXX` would be your name space. [2025-09-16 8:39 p.m.] tholin I'll probably be re-naming this to `gf180mcu_as_extra`, then. Its intended to mostly only contain non-synthesizable special cells anyways, that you have to instantiate explicitly (i.e. transmission gates). [2025-09-16 8:44 p.m.] mithro_ SGTM! [2025-09-16 9:10 p.m.] rebelmike Hi all, I've made a start getting TinyQV building on gf180 - shamelessly stole the build script from tinytapeout-gf-0p1. Result is here https://github.com/MichaelBell/gf180mcu-tinyQV {Embed} https://github.com/MichaelBell/gf180mcu-tinyQV GitHub - MichaelBell/gf180mcu-tinyQV: TinyQV for gf180mcu TinyQV for gf180mcu. Contribute to MichaelBell/gf180mcu-tinyQV development by creating an account on GitHub. 2025-09_media/gf180mcu-tinyQV-226D0 [2025-09-16 9:11 p.m.] rebelmike Fits in 600x600um with 25um padding. It's quite slow though, it wouldn't build with a 50MHz clock so I used 40MHz. Whereas it manages over 70 on sky130, is that expected? [2025-09-16 9:12 p.m.] tholin I've gotten pretty good at squeezing performance out of gf180 flows. Let me try. [2025-09-16 9:13 p.m.] tholin What is tinyQV again? [2025-09-16 9:14 p.m.] rebelmike Sure - though this is just me mucking about for now! Don't have any particular goal yet. [2025-09-16 9:14 p.m.] rebelmike TinyQV is my quad bit serial Risc-V CPU. Tim was looking for a small Risc-V CPU and we thought it might be a good fit [2025-09-16 9:16 p.m.] rebelmike Its latest outing was on the ttsky25a Risc-V peripheral competition - those versions are huge with loads of peripherals connected. But this version is just the "standard" one [2025-09-16 9:17 p.m.] tholin I...uhhh....I’ve never seen this happen before {Attachments} 2025-09_media/image-EE40A.png {Reactions} 😬 [2025-09-16 9:19 p.m.] mithro_ There is some stuff about Mike's TinyQV in my doc @ https://bit.ly/ws-tiny-riscv-proof {Embed} https://bit.ly/ws-tiny-riscv-proof wafer.space - GF180MCU Bit Serial RISC-V Implementation - bit.ly/ws... GF180MCU Bit Serial RISC-V Implementation https://bit.ly/ws-tiny-riscv-proof Goal The primary goal of this project is to show a potential pathway to creating “custom RISC-V” chips with wafer.space’s low volume manufacturing & chip on board packaging that are within the realm of being cost compet... 2025-09_media/AHkbwyLVub4Uei-LT5TnFCJAaungYRu8uZxoPy9gfP-3A9DC [2025-09-16 9:21 p.m.] 246tnt @RebelMike I would expect gf180 to be slower than sky130 yes, no doubt about it. With tweaking and optimizing, you could maybe get gf180 to match a "default run" of sky130 but if you put the same effort tweaking and optimizing, I'd expect sky130 to win speed wise. {Reactions} 👍 [2025-09-16 9:21 p.m.] mithro_ @RebelMike - Looks like you are using a bunch of flip flops for the register file? https://github.com/MichaelBell/gf180mcu-tinyQV/blob/main/src/latch_mem.v ? {Embed} https://github.com/MichaelBell/gf180mcu-tinyQV/blob/main/src/latch_mem.v gf180mcu-tinyQV/src/latch_mem.v at main · MichaelBell/gf180mcu-tinyQV TinyQV for gf180mcu. Contribute to MichaelBell/gf180mcu-tinyQV development by creating an account on GitHub. [2025-09-16 9:22 p.m.] mithro_ Or is that main memory? [2025-09-16 9:22 p.m.] rebelmike That is some scratch memory - though not actually included in that build above. [2025-09-16 9:23 p.m.] rebelmike Registers are just flip flops - they're in https://github.com/MichaelBell/tinyQV/blob/gf180mcu/cpu/register.v {Embed} https://github.com/MichaelBell/tinyQV/blob/gf180mcu/cpu/register.v tinyQV/cpu/register.v at gf180mcu · MichaelBell/tinyQV A Risc-V SoC for Tiny Tapeout. Contribute to MichaelBell/tinyQV development by creating an account on GitHub. 2025-09_media/tinyQV-4674D [2025-09-16 9:27 p.m.] rebelmike Would probably want to tweak the way this works a bit - all of the registers rotate constantly (idea came from https://github.com/Wren6991/tt02-whisk-serial-processor), but using a clock gate or plain enable in logic so only the registers being accessed are rotated would probably be preferable. [2025-09-16 9:35 p.m.] mithro_ @RebelMike - how does that build compare in size to the minimax example @Xobs did a long time ago pictured the doc @ https://bit.ly/ws-tiny-riscv-proof ? {Attachments} 2025-09_media/image-41F9D.png {Embed} https://bit.ly/ws-tiny-riscv-proof wafer.space - GF180MCU Bit Serial RISC-V Implementation - bit.ly/ws... GF180MCU Bit Serial RISC-V Implementation https://bit.ly/ws-tiny-riscv-proof Goal The primary goal of this project is to show a potential pathway to creating “custom RISC-V” chips with wafer.space’s low volume manufacturing & chip on board packaging that are within the realm of being cost compet... 2025-09_media/AHkbwyLVub4Uei-LT5TnFCJAaungYRu8uZxoPy9gfP-3A9DC [2025-09-16 9:39 p.m.] rebelmike Is that https://github.com/gsmecher/minimax ? I hadn't come across that before. {Embed} https://github.com/gsmecher/minimax GitHub - gsmecher/minimax: Minimax: a Compressed-First, Microcoded ... Minimax: a Compressed-First, Microcoded RISC-V CPU - gsmecher/minimax 2025-09_media/b48422f6-7d75-4c5a-a589-54efc82a55af-555BB [2025-09-16 9:46 p.m.] rebelmike Eyeballing that it looks like the area is around 200x400? But then there's the large register file. TinyQV takes the approach of supporting RV32EC with the absolute minimum number of writable registers to allow normal C code to work (just 13, as gp and tp can be hardwired without breaking the C ABI). [2025-09-16 9:56 p.m.] rebelmike TinyQV also supports interrupts and basic CSRs. I've also included UART, SPI and PWM peripherals in that build. I guess we would need to decide what should be included given the goal of demoing a "custom Risc-V chip". Maybe including one of the peripherals from the TT competition would make sense to show that custom design concept. Probably reducing the number of general purpose IOs makes sense as I imagine the pad space is going to be a limiting factor. [2025-09-16 9:58 p.m.] mithro_ @RebelMike - Yeah, I think that was the minimax CPU that @Xobs used. [2025-09-16 10:01 p.m.] mithro_ @RebelMike - I think 600um x 600um is only a bit bigger than the largest SRAM block size? {Attachments} 2025-09_media/image-15E84.png [2025-09-16 10:07 p.m.] mithro_ @RebelMike - Seems like you could fit somewhere like ~40ish copies on a single wafer.space slot? {Attachments} 2025-09_media/image-760BD.png [2025-09-16 10:11 p.m.] rebelmike Sounds plausible - the 600x600 was just my initial guess, though I did have to work a little to make the build pass I'm sure it could go a bit smaller (but then we'd probably decide we wanted to include more things anyway). Taking a peak at @urish's setup for Tiny Tapeout on gf180, 2x2 tiles is 711.20x325.36 - so if that's roughly equivalent to 2x2 tiles on sky130 it should be possible to squeeze it into that area. [2025-09-16 10:13 p.m.] rebelmike Hmm, actually that is quite a lot smaller so that might be a challenge. [2025-09-16 10:15 p.m.] mithro_ >40 is much bigger than >20 that doc was potentially thinking about. [2025-09-16 10:21 p.m.] mithro_ I had some data about Tiny Tapeout tile sizes and capacities in the spreadsheet @ https://docs.google.com/spreadsheets/d/1hgfRhANt3jyG4w0tgVumoxdqkyLpXQksTHPXk9g4_NM/edit?gid=924741324#gid=924741324 -- That was from quite a long time ago, so don't know if it matches / got updated with the latest configs. {Embed} https://docs.google.com/spreadsheets/d/1hgfRhANt3jyG4w0tgVumoxdqkyLpXQksTHPXk9g4_NM/edit?gid=924741324 Tiny Tapeout Sizing Comparisons 2025-09_media/AHkbwyKTMijXzaANNwofCXLWnYQyRHjerus3bpcnIs-2C152 [2025-09-16 10:22 p.m.] rebelmike That does assume no (or maybe minimal) on chip cache/RAM. Performance is therefore not amazing. [2025-09-16 10:23 p.m.] mithro_ Well, you might be able to add a 512 bytes SRAM to your config and still fit 20 versions.... {Reactions} 👍 [2025-09-16 10:24 p.m.] rebelmike Big unknown for me is pad size. Looks like the TT test chip is using 355x75 with 20.3 spacing. That could mean pads are a larger area than the CPU [2025-09-16 10:29 p.m.] mithro_ @RebelMike - I think the first subdivision configuration is probably just going to be 1/2 or 1/4, so you'll have plenty of space. {Reactions} 👍 [2025-09-17 12:17 a.m.] xobs Yeah, one of the downsides to the minimax was that you need two copies of the register file so it could bank everything in case of an unhandled instruction. [2025-09-17 7:48 a.m.] rebelmike Makes sense on FPGA, but expensive on asic. [2025-09-17 8:22 p.m.] rebelmike Some thoughts on size for meeting the eventual goal, and approach to getting TinyQV into a suitable state to enable that, here: https://docs.google.com/document/d/16-JBqH7T6T0cKGpoZkjNh42dn7F8hudmymY-CGiME2c/edit?usp=sharing {Embed} https://docs.google.com/document/d/16-JBqH7T6T0cKGpoZkjNh42dn7F8hudmymY-CGiME2c/edit?usp=sharing TinyQV gf180mcu TinyQV as custom Risc-V demo Goal Show it’s possible to create custom Risc-V chips at reasonable cost on wafer.space. Tim’s doc has more: https://docs.google.com/document/d/1U5tQairqGWx1kK3jr6FB_aSNz2RWzo8jpJg-MWs9UXI/edit?tab=t.0 Preparatory work Aim is to get TinyQV into a state where it ma... 2025-09_media/AHkbwyLuz04cEgCPI2rMB0Z62l0OAk1Gv3-17BRRn4-71A39 [2025-09-18 9:47 p.m.] mithro_ Yeah, minmax was targeting FPGAs where blockram is pretty cheap [2025-09-18 9:58 p.m.] mithro_ I updated the wafer-space GitHub organization at with a little more content https://github.com/wafer-space {Embed} https://github.com/wafer-space wafer.space Budget silicon manufacturing -- create integrated circuits without breaking the bank. - wafer.space 2025-09_media/206372765-BA965 {Reactions} 👍 [2025-09-19 4:21 a.m.] urish Looks good [2025-09-19 4:21 a.m.] mithro_ Slowly updating the website - https://preview.wafer.space/pr-44/ {Embed} https://preview.wafer.space/pr-44/ wafer.space - Budget silicon manufacturing. Create integrated circuits without breaking the bank! [2025-09-19 5:10 a.m.] mithro_ I also did an interview today with Chris Gammell for the Amp Hour, challenged him to do a Tiny Tapeout before the next time I'm on his podcast 🙂 - I believe it should be live late next week sometime. {Reactions} ❤️ [2025-09-19 5:33 a.m.] urish Nice countdowns! [2025-09-19 9:07 a.m.] mole99 I'm glad to announce the wafer.space template! https://github.com/wafer-space/gf180mcu-project-template {Embed} https://github.com/wafer-space/gf180mcu-project-template GitHub - wafer-space/gf180mcu-project-template: Project template fo... Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template 2025-09_media/gf180mcu-project-template-97D29 {Reactions} 🎉 (4) [2025-09-19 9:07 a.m.] mole99 The template is a work in progress, so further changes are to be expected. There is an issue with resizing in OpenROAD because the I/O library specifies a fanout of 1, therefore we have to wait for a fix to re-enable resizing. However, your design may not be affected. Just enable resizing in the config file and see for yourself. Filler generation may change in the future, however it should already be possible to meet the target densities. DRC with magic is currently failing. There are some unknown layer/datatypes, and we need to either fix the DRC errors in the I/O cells or exclude them during DRC. [2025-09-19 9:07 a.m.] mole99 Despite these issues you can already use it to implement your design. Please give it a try and let me know how it goes! I've also added a wrapper around the dvdd/dvss pads to allow them to be placed in the eastern and western rows of the padring. For now feel free to change the padring as you like. [2025-09-19 9:08 a.m.] mole99 As a next step, I would need the final pad positions for the padring from Tiny Tapeout ( @tnt ). These positions will be the same for all wafer.space customers (if they opt for packaging). It is possible to change I/O types such as input/output/bidir, but the power/ground pads should stay the same, as they will be bonded to power/ground rings in the case of CoB and to the ground pad in the case of QFN. [2025-09-19 9:19 a.m.] 246tnt @Leo Moser (mole99) Drafting something now ... [2025-09-19 9:20 a.m.] algofoogle This is pretty exciting! How many pads are you going for? [2025-09-19 9:21 a.m.] algofoogle Fantastic, Tim! Can’t wait to hear it, and I hope he does do a submission! I was thinking Dave Jones should do one too. [2025-09-19 9:24 a.m.] 246tnt Well for TT the target when packaged is QFN64. What I'm drafting now will have 74 bond pads since 10 of those will be GND and will only go to the EPAD. 6 will be power so that leaves 58 "user" connections. [2025-09-19 9:26 a.m.] tholin What I’m drafting is just a copy of the caravel pad-out, but the SPI flash pins become extra user GPIO. [2025-09-19 9:27 a.m.] tholin Since I’m targeting a DIP-40 footprint, that is sufficient IO. [2025-09-19 9:29 a.m.] mole99 @Tholin Yes, but you'll have to map this to the Tiny Tapeout padring before your final submission if you want packaging. Some of your unused pads could be used for debugging functionality. [2025-09-19 9:32 a.m.] 246tnt Of course if you just want raw dies and handle all packaging yourself, you do whatever you please. [2025-09-19 9:33 a.m.] mole99 Absolutely. [2025-09-19 9:36 a.m.] algofoogle This sounds pretty cool. Just that bit more flexibility than OpenFrame [2025-09-19 9:40 a.m.] tholin I’m probably going to have to do packaging myself if I want to bond to DIP PCB carriers [2025-09-19 9:43 a.m.] mole99 I think there was a discussion about providing your own PCBs (with the same CoB footprint?) somewhere. @Tim 'mithro' Ansell will know. [2025-09-19 9:47 a.m.] tholin The PCBs may also have project-specific components on them [2025-09-19 9:47 a.m.] tholin Or it may not even be DIP-40, but something smaller, like DIP-28 (the wide one) [2025-09-19 9:48 a.m.] tholin Or some pins need to be bonded differently [2025-09-19 9:48 a.m.] tholin So there is no one size fits all PCB layout for me. This is the downside of making a multi-project die. [2025-09-19 9:48 a.m.] tholin And why I am desperately trying to hunt down a wire bonder for myself. [2025-09-19 10:00 a.m.] mole99 That's why a carrier board (like on Tiny Tapeout) is a good idea. But if that doesn't work for you, you'll have to go the manual route. [2025-09-19 10:05 a.m.] tholin I’m pretty space constrained by having to fit the dimensions of those DIP footprints [2025-09-19 10:12 a.m.] 246tnt @Leo Moser (mole99) https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?usp=sharing {Embed} https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?usp=sharing TT GF180 padframe 2025-09_media/AHkbwyKYbpWB-91BLdfVeiyR-EDy0Jp2F1tCOeZ1We-12A32 [2025-09-19 6:42 p.m.] mole99 Started a thread. [2025-09-19 6:52 p.m.] mithro_ Seems like everyone has been quite busy while I've been sleeping! [2025-09-19 11:42 p.m.] rebelmike @Leo Moser (mole99) Is https://github.com/wafer-space/gf180mcu-project-template/blob/main/config.yaml#L165 correct? I think it should either be 25 more, to account for the seal ring on both sides, or exactly 5070x3880 if seal ring is added externally. [2025-09-20 7:46 a.m.] mole99 Good catch! I tested the reticle stitcher with my GF-MPW1 project, where I added the sealring externally. I've now updated the project template. {Reactions} 👍 [2025-09-20 8:18 p.m.] mithro_ @urish / @Matt Venn - After I get the website updated with the campaign content, I would like to get Tiny Tapeout collaboration information up on the websites. {Reactions} 👍 (2) [2025-09-20 9:14 p.m.] mattvenn Fyi I'm travelling next week for austrochip [2025-09-21 3:01 a.m.] mithro_ The website @ https://wafer.space has now been updated quite a bit, nothing new compared to the campaign page. {Embed} https://wafer.space/ wafer.space - Budget silicon manufacturing. Create integrated circuits without breaking the bank! [2025-09-21 4:09 a.m.] urish Started a thread. [2025-09-21 3:21 p.m.] tholin So, if I followed the conversation about tiny RISC-V cores on GF180 so far, the biggest constraint so far appears to be the size of the register file, which actually becomes larger than the CPU core itself at some point. Has it been considered yet that the registers can be moved into RAM? Reserve 32 words of RAM to hold the register values. [2025-09-21 7:28 p.m.] rebelmike Started a thread. [2025-09-22 3:35 p.m.] mole99 I just updated the project template to limit the sealring generator to Metal5 and add `MAGIC_GDS_FLATGLOB` to the LibreLane config. The remaining issues during DRC are because of some missing layer definitions, duplicate cell entries, and overlapping cuts (which is annoying to fix as per Tim 😅). You can update your local copy py simply pulling the latest changes and running `make clone-pdk` again. [2025-09-23 5:23 p.m.] mithro_ @Leo Moser (mole99) - Should that fix https://github.com/wafer-space/gf180mcu-project-template/issues/1 ? {Embed} https://github.com/wafer-space/gf180mcu-project-template/issues/1 Encountered one or more fatal errors while running Magic. · Issue ... Ran make clone-pdk, then nix-shell then make librelane ends up with the following error; Generating output for cell chip_top [INFO] GDS Write Complete Classic' - Stage 57 - GDSII Stream Out (Ma... 2025-09_media/1-8D505 [2025-09-23 6:00 p.m.] mole99 Streamout should already work, it may be that the template was in a weird state. Can you pull the latest changes and clone the PDK again? I've also now subscribed to the repo so I get notifications for the issues. Let's continue on GitHub if you get the same issue again. [2025-09-23 6:42 p.m.] mithro_ Just tried again, got the same error I think..... [2025-09-24 9:08 a.m.] mole99 Replied to your issue with a solution. [2025-09-24 2:46 p.m.] mithro_ Not sure you actually replied with a solution but I'm testing what I think you meant 🙂 [2025-09-25 10:14 a.m.] mattvenn Nice amp hour interview @Tim 'mithro' Ansell ! {Reactions} 💯 [2025-09-25 10:25 a.m.] urish Started a thread. [2025-09-25 10:56 a.m.] anfroholic https://theamphour.com/703-building-wafer-space-with-tim-ansell/ {Embed} https://theamphour.com/703-building-wafer-space-with-tim-ansell/ #703 – Building wafer.space with Tim Ansell | The Amp Hour Electr... Tim 'Mithro' Ansell returns to The Amp Hour to discuss his new Singapore based wafer sharing service called wafer.space. Now that eFabless is no more, this venture will aim to make silicon even more accessible to the masses, driving down the costs on a per chip basis. For $7K, you get 1000 chips delivered on a 180 nm process from Global Foundries. [2025-09-25 11:50 p.m.] rtimothyedwards_19428 @Tholin : Would `lctime` be able to create timing files for an I/O library? [2025-09-25 11:51 p.m.] tholin Probably not [2025-09-26 1:36 a.m.] mithro_ I'll also be on Teardown Sessions next week on the 3 Oct 2025 @ 2:00pm Chicago (other regions https://bit.ly/teardown-session-waferspace-1) - https://www.youtube.com/watch?v=tEOmnN8IAjs {Embed} https://bit.ly/teardown-session-waferspace-1) The World Clock Meeting Planner - Details Local time for a meeting, in user selected locations. 2025-09_media/meeting-planner-95506.png {Embed} Crowd Supply https://www.youtube.com/watch?v=tEOmnN8IAjs Teardown Session 56: wafer.space with Tim Ansell Join Crowd Supply's Helen Leigh for a conversation with Tim Ansell about wafer.space. About Crowd Supply Crowd Supply is the crowdfunding platform of choice for engineers, hackers, designers, and idealists. We help them with the funding and support they need to deliver respectful, thoughtfully crafted, open source hardware to their delighted ba... 2025-09_media/maxresdefault_live-743AB.jpg [2025-09-26 8:16 a.m.] h.tamas Started a thread. [2025-09-26 9:35 a.m.] algofoogle Great Amp Hour interview @Tim 'mithro' Ansell 🙂 I feel like hassling Chris to get serious about doing a TT submission {Reactions} ❤️ (2) [2025-09-26 1:18 p.m.] mithro_ Do it 🙂 {Reactions} 💪 [2025-09-26 1:34 p.m.] mattvenn I'll try as well [2025-09-27 8:19 p.m.] tholin In about 30 minutes I'll be taking the virtual stage to hold a presentation entitled "How NOT to design an integrated circuit", the synposis for which is `From low-level programming to now making her own integrated circuits, Tholin is a seasoned member of the Open-Source-Silicon community. Tholin has a record-breaking 8 tapeouts under her belt. In this presentation, we'll gloss over all the successes and present all the failures and mistakes that were made over those tapeouts to learn what to avoid and not to do when taking on such ambitious projects.` {Reactions} 💜 (2) [2025-09-27 8:20 p.m.] tholin I'll be recording the whole thing [2025-09-28 2:47 a.m.] tholin I made my own recording that has better audio from my mic. Threw it up on my fileserver for now. Like 75% of the presentation is about my experiences with GFMPW-0/1. https://files.tholin.dev/Public/Videos/dgt_2025_09_27.mp4 {Reactions} 💜 (2) [2025-09-28 8:32 p.m.] mithro_ @Tholin - Cool, I'll give it a watch later today. [2025-09-29 1:46 a.m.] mithro_ @Tholin - Great presentation! It's awesome that you didn't give up after the first few problems. It also looked like you managed to have some type of work arounds for a lot of issues? [2025-09-29 7:46 a.m.] tholin I am incredibly persistent [2025-09-29 7:46 a.m.] tholin I worked around most problems. [2025-09-29 3:54 p.m.] h_thoreson_71412 I have work so it will take me a bit to get through but watching around other meetings and obligations [2025-09-29 3:58 p.m.] mithro_ @Tholin - I would love to hear the gritty details about how exactly you worked around all the various problems. There is a pretty strong history of people in "our" community getting things working that industry have declared impossible (Another example of @tnt managing to the very early MPW chips going) and I would like to keep driving that home. [2025-09-29 6:21 p.m.] tholin Well, firstly, figuring out what is even going wrong and why is the hard part. [2025-09-29 6:22 p.m.] tholin Only then can you look at what you have and see if you can't nudge things in the right direction again. [2025-09-29 6:24 p.m.] tholin I'm always very happy when I can fix things in software. [2025-09-29 6:27 p.m.] tholin For the AS-11, it just needed a custom assembler frontend to handle the differences in bytecode from the PDP-11/40. [2025-09-29 6:27 p.m.] tholin I say "just" as in, it was a logically simple solution, but took a while to actually implement. [2025-09-29 6:29 p.m.] tholin The VLIW icache actually works under certain conditions. The fetches only fail if the icache contains any instruction packs that have breaks set. So break-free code can be cached safely. So all the software I've written for VLIW, I turn the icache on for loops where its safe and then back off, which still boosts performance decently. [2025-09-29 6:30 p.m.] tholin QCPU is the most exciting story from a hardware perspective, AS2650-1 from a software perspective. [2025-09-29 7:18 p.m.] h_thoreson_71412 This is really interesting. It kind of answered one of the lingering questions I've had about how people are using TT to do more sophisticated designs - there's an existing testing framework somewhere? [2025-09-29 9:51 p.m.] mithro_ @h_thoreson - @Tim Edwards was also telling me about his usage of an Arty A7 FPGA board I sent him for some TT and GF180MCU testing. {Reactions} 👍 [2025-09-29 9:54 p.m.] h_thoreson_71412 Interesting - I have one of those but I haven't used it in ages. Hopefully it still works 😅 [2025-09-30 1:35 a.m.] mithro_ I've merge the Design Help page into the wafer.space website, so https://wafer.space/design-help.html now exists. {Embed} https://wafer.space/design-help.html Design Help Budget silicon manufacturing. {Reactions} 👀 [2025-09-30 1:41 a.m.] mithro_ @Tholin - If you want Avalon Semiconductors listed there, 100% happy to add it. [2025-09-30 3:50 a.m.] mithro_ Started a thread. [2025-09-30 5:42 a.m.] mithro_ @Leo Moser (mole99) and myself will be on Crowd Supply's Teardown Session talking with Helen about wafer.space this Thursday (2nd October) - http://youtu.be/tEOmnN8IAjs {Embed} Crowd Supply https://www.youtube.com/watch?v=tEOmnN8IAjs Teardown Session 56: wafer.space with Tim Ansell & Leo Moser Join Crowd Supply's Helen Leigh for a conversation with Tim Ansell about wafer.space, a new way for chip designers to easily turn a design into real, working chips. *About Our Guests* Tim “mithro” Ansell builds the bridges that make open silicon real. At Google, he helped release the SkyWater SKY130 open-source PDK and launched the Open MPW... 2025-09_media/maxresdefault_live-743AB.jpg {Reactions} 👍 (3) [2025-09-30 7:42 a.m.] tholin Not yet, unless you want to list my GFMPW-1 submissions as example projects (which you totally can). I am more interested in contributing to writing that Documentation mentioned towards the bottom of the page. [2025-09-30 12:06 p.m.] vipul.sh @Tim 'mithro' Ansell Are there any reference materials or guides available for using GF180 PDK with open-source EDA tools especially for analog design ? Compared to SKY130, there appears to be lack of such publicly accessible resources for GF180. [2025-09-30 12:06 p.m.] vipul.sh Any suggestions how to start exploring designs with GF180? [2025-09-30 12:09 p.m.] tholin Its been a while since I went in-depth with sky130 - what resources for sky130 are you referring to? [2025-09-30 12:21 p.m.] vipul.sh By resources, I am referring to youtube tutorials or publicly available reference flows on platforms like github that can help newcomers get started with a specific PDK (GF180 in this case) and its integration into analog design tools such as xschem, ngspice, magic, netgen. [2025-09-30 12:22 p.m.] vipul.sh Analog design using open-source tools is far less streamlined than RTL-to-GDS flow available for digital design with Openlane. [2025-09-30 12:24 p.m.] tholin Ah, analog design guides for gf180 was something that I was missing. I’ve since figured it out on my own, but it took a bit. [2025-09-30 5:22 p.m.] mithro_ Welcome @Vipul - You are correct that GF180MCU resources are a lot more limited than SKY130. We only had 2 free MPW runs for GF180MCU compared to the 8 for SKY130 and until wafer.space there was no easy way to pay to get access to GF180MCU manufacturing (unlike SKY130 which had chipIgnite). Hopefully you can help change that now that GF180MCU is more available. [2025-09-30 5:23 p.m.] mithro_ I believe the IEEE SCSS Chipathon has a bunch of resources but I can never find the right link to use [2025-09-30 5:23 p.m.] mithro_ https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-design-contest/ {Embed} kressel@thinkdm2.com https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-design-contest/ SSCS “PICO” Open-Source Chipathon - IEEE Solid-State Circuits S... SSCS is pleased to announce its 4th open-source integrated circuit (IC) design contest under the umbrella of its PICO Program. [2025-09-30 5:24 p.m.] mithro_ And/or https://github.com/sscs-ose/sscs-chipathon-2025 ? {Embed} https://github.com/sscs-ose/sscs-chipathon-2025 GitHub - sscs-ose/sscs-chipathon-2025: Blocks & Bots: An Open Chip ... Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-design-contest/ - sscs-ose/sscs-chipathon-2025 2025-09_media/sscs-chipathon-2025-6FDCC [2025-09-30 5:31 p.m.] vipul.sh Sure @Tim 'mithro' Ansell I will try to work on establishing custom analog design flow with as suggested by @Leo Moser (mole99) and put my queries here wherever I get stuck. Hopefully this will help to streamline the flow with open source analog tools for gf180. {Reactions} ❤️ [2025-09-30 5:34 p.m.] mithro_ All help is welcome! There are also multiple different ways to do things, so having people give it a go is important. [2025-09-30 5:37 p.m.] mithro_ lol - Since launching wafer.space, I'm now getting spam for high-purity fused silica quartz boats to my info email address! {Reactions} 😄 ============================================================== Exported 214 message(s) ==============================================================